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Inter-integrated circuit (I 2 C) interface
Table 171. I 2 C Interrupt requests (continued)
RM0008
Interrupt event
Bus error
Arbitration loss (Master)
Acknowledge failure
Overrun/Underrun
PEC error
Timeout/Tlow error
SMBus Alert
Event flag
BERR
ARLO
AF
OVR
PECERR
TIMEOUT
SMBALERT
Enable Control bit
ITERREN
Note:
24.5
640/995
1
2
SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.
Figure 237. I 2 C interrupt mapping diagram
ITEVFEN
SB
ADDR
ADD10
STOPF
it_event
BTF
TxE
ITBUFEN
RxNE
ITERREN
BERR
ARLO
it_error
AF
OVR
PECERR
TIMEOUT
SMBAlert
I 2 C debug mode
When the microcontroller enters the debug mode (Cortex-M3 core halted), the SMBUS
timeout either continues to work normally or stops, depending on the
Doc ID 13902 Rev 9
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